1. Field of the Invention
The present invention relates to a technology for generating a timing signal to drive a line image sensor.
2. Description of the Related Art
FIG. 23 is a timing diagram of typical timing signals, or clocks, that are used to drive a charge coupled device (CCD). The timing signals required to drive the CCD include an XPH1 and an XPH2 for transferring a signal charge obtained from a photodiode using an analog shift resistor, an XRS that resets a floating capacitor of a source follower with respect to each pixel, where the source follower converts the transferred signal charge into voltage and outputs the voltage from the CCD, an XCP that determines an offset level of a waveform to be output from the CCD, an XPH2L required at the last stage of transferring the charge, and an XSH that transfers the charge accumulated in the photodiode to the analog shift resistor in a period between exposure times.
These clocks are generated by a timing generator (TG). In the TG, a quartz oscillator produces a reference oscillations and a phase locked loop (PLL) multiplies the reference oscillations thereby adjusting the reference oscillations to have a required phase and a required pulse width. The clocks generated by the TG are passed through a driver before reaching the CCD.
Normally, the clocks including the XPH1, the XPH2, the XCP, the XRS, and the XPH2L are not constantly output. That is, these clocks are suspended for a predetermined period before or after a timing of the XSH. However, strict restrictions are set for the period of the suspension and the state of starting and ending the clock, which complicates the timing of the suspension. The restrictions vary delicately with the type of the CCD.
To cope with such restrictions, the conventional TG realizes an output of the timing signal virtually specific to each type of the CCD by making an application specific integrated circuit (ASIC) with the CCD determined at the stage of designing an apparatus (see, for example, Japanese Patent Application Laid-open No. 2006-340117). However, with the ASIC, the clock can be suspended only by masking a predetermined area of the ASIC before and after a predetermined gate signal. Therefore, if the timing specification of the CCD is changed, the TG cannot be used anymore, and a new ASIC needs to be developed.
Thus, there was a need of a timing generator that can generate a timing signal synchronized with a predetermined cycle based on a reference clock in image sensors having different timing specifications.